The present invention relates to imaging electronics in general, and more particularly to noise floor reduction in CMOS process Active Pixel image sensor systems.
CMOS process Active Pixel Sensor (APS) technology is foreseen as the next generation technology for image sensors, which will replace the currently dominating CCD technology. Among the advantages that APS technology has over CCD technology are the ability to integrate image sensor and camera electronics onto a single chip, low power dissipation due to the inherently lower CMOS process voltage as compared with CCD voltage, and significantly-lower manufacturing costs.
Dramatic advance in the CMOS process technology are also expected to lead to the implementation of imagers with a 5 xcexcm pixel pitch on a submicron CMOS process, which is approximately equal to the diffraction limit of the camera lens. This limit offsets one of the major advantages of CCD technology, namely the high fill factor afforded by a very simple pixel circuit.
The ability to implement photographic-quality imagers using CCD technology is severely limited by the large array dimensions that would be required, having thousands of pixel columns and rows. It is difficult to implement such large arrays using CCD technology due to the CCD Charge Transfer Efficiency (CTE) factor which dictates that image quality severely deteriorates as the size of the image sensor array increases. It is not commercially feasible to produce 3,000xc3x972,000 pixel CCD arrays as would be required for near photographic quality images due to the prohibitive manufacturing costs involved.
Although the transition from CCD-based technology to APS-based technology for commercial image sensors appears inevitable, APS technology has several limitations that have yet to be overcome. The ability to implement large CMOS-based APS image sensor arrays is limited by readout bus capacitance that originates from multiplexing all pixels within each column into a single column line. The parasitic output capacitances of the multiplexing circuits and of the line interconnect, normally implemented with metal, are the major contributors to column capacitance. Thus, for a given CMOS process and pixel unit cell size, the column capacitance is proportional to the number of multiplexed rows.
The column capacitance is the dominant contributor to the input-referred noise, and it governed by the so-called xe2x80x9ckTCxe2x80x9d noise mechanism. One technique that may be used to reduce the kTC noise effect involves introducing an amplification stage in each pixel""s unit cell by including an in-pixel Source-Follower circuit. The Source-Follower amplifier xe2x80x9cde-couplesxe2x80x9d the in-pixel integration capacitor from the column capacitance, which results in a reduced input-referred readout noise. However, this technique leads to a reduction in gain due to the attenuation of the signal as a function of column bus capacitance. This can be costly in terms of signal-to-noise ratio (SNR) for large-format circuits with a high column capacitance and for applications where the charge that is involved is small. Thus, although implementing a Source-Follower circuit results in a reduced input-referred readout noise, its effect diminishes as the imager""s size increases due to the increasing column capacitance.
The present invention seeks to provide methods and apparatus for noise floor reduction in CMOS-based APS image sensor arrays that overcomes disadvantages of the prior art. The present invention substantially reduces the column capacitance in large image sensor arrays, resulting in a reduced noise floor and a better signal-to-noise ratio. A Direct Injection (DI) circuit approach is employed in place of the Source-Follower circuit per unit cell approach. A DI circuit is relatively simple to implement and deploys less transistors per unit cell, which results in a higher unit cell fill-factor, a smaller pixel, or both. Furthermore, the Fixed Pattern Noise (FPN) of a DI circuit is considerably lower than that of the Source-Follower-based unit cell. The DI circuit of the present invention directly injects the charge accumulated by the integration capacitor into the column. This results in a significant input-referred readout noise that is higher than that of the Source-Follower-based unit cell. By reducing column capacitance the present invention significantly reduces the image sensor""s noise floor and improves its signal-to-noise ratio, particularly in large image sensor arrays.
In one aspect of the present invention an image sensor array is provided including a first plurality of unit cells coupled to a first sense amplifier, and a second plurality of unit cells coupled to a second sense amplifier, where the first plurality and the second plurality are substantially electrically isolated from each other.
In another aspect of the present invention each of the first and second pluralities of unit cells includes at least one column line.
In another aspect of the present invention the unit cells are arranged in two or more clusters of two or more of the unit cells each, and the unit cells within each of the clusters are coupled to a cluster line which is coupled to the column line.
In another aspect of the present invention only one of the clusters is actively connected to the column line at any given time.
In another aspect of the present invention the unit cells are direct injection unit cells.
In another aspect of the present invention the first plurality and the second plurality are substantially electrically isolated from each other by at least 10M Ohms.
In another aspect of the present invention an image sensor array is provided including a plurality of columns, each column including a plurality of unit cells coupled to a column line, a first sense amplifier coupled to a first plurality of the unit cells in each of the columns, and a second sense amplifier coupled to a second plurality of the unit cells in each of the columns, where the first and second pluralities of the unit cells in each of the columns are substantially electrically isolated from each other.
In another aspect of the present invention each of the columns includes a plurality of clusters, each cluster including two or more of the unit cells coupled to a cluster line which is coupled to the column line.
In another aspect of the present invention only one of the clusters is actively connected to the column line at any given time.
In another aspect of the present invention the unit cells are direct injection unit cells.
In another aspect of the present invention the first plurality and the second plurality are substantially electrically isolated from each other by at least 10M Ohms.
In another aspect of the present invention a method for reducing noise floor in an image sensor is provided, the method including sensing a first plurality of unit cells with a first sense amplifier; and sensing a second plurality of unit cells with a second sense amplifier.
In another aspect of the present invention either of the sensing steps includes sensing different subsets of the unit cells at different times.
In another aspect of the present invention either of the sensing steps includes sensing mutually exclusive subsets of the unit cells at different times.
In another aspect of the present invention each of the sensing steps includes sensing its associated plurality of unit cells in substantial electrical isolation from the other the plurality of unit cells.
In another aspect of the present invention each of the sensing steps are performed alternatingly.
The disclosures of all patents, patent applications, and other publications mentioned in this specification and of the patents, patent applications, and other publications cited therein are hereby incorporated by reference in their entirety.